Cross-sectional SEMs of trench structures show that as the pitch of the device increases greater than 1.5 xcexcm, the sidewall profiles can change from a favorable to a non-favorable, re-entrant shape, as shown by a comparison of FIGS. 1 and 2. FIG. 1 depicts a trench device structure 100 whose etched trenches 101 have a pitch of 1.5 xcexcm. Trenches 101 are lined with gate oxide 102 and filled with doped polysilicon 103 and BPSG dielectric 104. When the pitch is 1.5 xcexcm or less, the filled trenches exhibit void-free fills. Such trench structures are found in integrated circuits and are used for isolation and for gates in quasi vertical DMOS (QVDOMS) devices.
As the pitch increases greater than 1.5 xcexcm, the trench profile becomes re-entrant, i.e., the sidewalls become non-parallel as a consequence of insufficient oxygen being present during plasma etching of the trenches. FIG. 2 depicts a trench device structure 200 whose etched trenches 201 have a pitch of 3.0 xcexcm. Trenches 201 are lined with gate oxide 202 and filled with doped polysilicon 203 and BPSG dielectric 204. However voids resulting from incomplete fill are formed in the subsequent polysilicon and BPSG films 203 and 204, respectively, which adversely affects device yield. In particular, the voids lead to rupture of the gate oxide, resulting in shorting of gate-to-source current (Igss). FIG. 3 shows a BPSG film 204 with voids 205 that lead to an Igss failure.
Lateral etching of the silicon during trench formation is commonly referred to as xe2x80x9cbowingxe2x80x9d. The bowing effect of lateral etching is shown in FIG. 2, where the upper portions 201a of trenches are substantially narrower than the lower trench portions 201b. 
The present invention is directed to a method for forming trenches in a device layer disposed on a silicon semiconductor substrate. The method comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts with time, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.